Look at a photograph of one of IBM's quantum processors and you might expect a dense mesh, every qubit wired to as many neighbors as possible. Instead you find something that looks almost stingy: a honeycomb of hexagons with qubits perched on the edges, most of them connected to just two partners, a few to three. This is the heavy-hexagonal lattice, and IBM has built its chips around it since the Falcon generation, carrying it forward through Eagle, Osprey, Condor, and the Heron processors that anchor the company's current fleet.
The sparseness is not an accident or a manufacturing limitation. It is a considered trade, and understanding it explains a lot about why superconducting quantum computers look the way they do.
The problem with crowded qubits
Superconducting transmon qubits talk to their neighbors through fixed physical couplings. That connectivity is what lets you entangle two qubits and run a two-qubit gate, the workhorse operation of nearly every quantum algorithm. More connections sounds better: shorter paths between any two qubits, fewer detours when a circuit needs distant qubits to interact.
But every connection is also a liability. Transmons are distinguished by their operating frequencies, and when two coupled qubits sit too close in frequency they can leak information into each other or trigger unwanted interactions. Chip designers call these frequency collisions, and they get harder to avoid as the number of neighbors climbs. A qubit with four or six neighbors has to thread a much tighter frequency needle than one with two. Fabrication scatter, the small variation from qubit to qubit that no fab can fully eliminate, makes collisions statistically likely once connectivity is high.
There is also crosstalk. When you drive one qubit with a control pulse, nearby qubits feel a faint echo. The more neighbors a qubit has, and the more of them are being driven at once, the more spurious errors accumulate on bystanders. Engineers sometimes call these spectator errors. In a densely packed grid, running a gate on one pair can quietly corrupt the qubits sitting next to it.
Trading paths for peace
The heavy-hex layout attacks both problems at their source by simply reducing the number of neighbors any qubit can have. Cap the connectivity at three, and often just two, and the frequency-assignment puzzle becomes tractable. Collisions grow rarer. Crosstalk drops because each qubit has fewer chattering companions. The lattice also spaces things out enough that IBM can slot control and readout hardware in without the whole assembly interfering with itself.
The cost is routing. If your algorithm needs two qubits on opposite sides of the chip to interact, they cannot simply reach across the empty space. The compiler has to move quantum information step by step using SWAP operations, each of which is itself built from two-qubit gates and adds error. A dense grid would need fewer of these detours. Heavy-hex needs more, which lengthens circuits and eats into the fidelity budget.
IBM's wager is that the trade pays off. A sparse chip where every gate is clean beats a dense chip where gates are noisy and frequencies constantly collide, especially at scale. When you are trying to build a processor with hundreds or thousands of qubits, a layout that keeps yield high and collisions manageable is worth the extra routing overhead. The company's transpiler software has grown steadily better at finding efficient paths through the honeycomb, softening the penalty.
Why the shape matters for error correction
The choice has consequences beyond raw gate counts. Quantum error-correcting codes have their own connectivity appetites. The surface code, the most studied scheme, wants a square grid of qubits each touching four neighbors, which is more than heavy-hex naturally provides. That mismatch is one reason IBM has invested heavily in codes better suited to sparse hardware, including the low-density parity-check codes that gave rise to its bicycle-style layouts. The lattice you etch into silicon shapes which error-correcting strategies stay practical later.
It is a reminder that a quantum processor is not just a pile of qubits. The pattern in which they are wired together reflects a chain of compromises among fabrication yield, crosstalk, frequency crowding, routing cost, and the demands of future error correction. Heavy-hex is one answer to that puzzle. The empty space in the honeycomb is doing real work, buying quieter qubits at the price of longer journeys between them.
