Most companies in quantum computing talk in milestones. IBM talks in machines with names. Its published roadmap reads like a flight plan, each stop a specific processor or system meant to settle one hard question before the next one gets tackled. The destination is a system IBM calls Starling, intended to be a large, error-corrected quantum computer rather than a noisy experiment. Understanding the roadmap means understanding why the company thinks it can get there in stages instead of one giant leap.
Why a roadmap at all
Building a fault-tolerant quantum computer is not one problem. It is a stack of problems that each depend on the one below. You need qubits that live long enough. You need to wire up control electronics without drowning the chip in cables. You need an error-correcting code that does not demand an absurd number of physical qubits per logical one. And you need a way to connect modules so the machine can grow past the limits of a single chip. Solve any one in isolation and you still do not have a computer. A roadmap is IBM's way of sequencing those dependencies so that each new processor tests a specific piece without betting the whole program on it.
The shift to qLDPC codes
The most consequential choice in the plan is the error-correcting code. For years the default assumption was the surface code, which is robust but hungry, often needing on the order of a thousand physical qubits to protect one logical qubit well enough for deep algorithms. IBM has thrown its weight behind a different family known as quantum low-density parity-check codes, and specifically a variant sometimes called the bivariate bicycle code. The appeal is efficiency. These codes aim to protect logical information with roughly ten times fewer physical qubits than a comparable surface-code layout, which turns an impossible qubit count into a merely difficult one.
The catch is connectivity. qLDPC codes require some qubits to talk to partners that are not their immediate neighbors on the chip. That means longer couplers and a more intricate wiring geometry than IBM's older heavy-hex grid was built for. A big part of the roadmap is dedicated to proving that those long-range connections can be built and operated without wrecking qubit quality.
The stepping stones
The plan names several processors, each with a job to do:
- A test chip whose purpose is to demonstrate the exotic couplers and the components a qLDPC code needs, essentially a proving ground for the code's hardware demands.
- Processors that focus on running useful circuits at larger scale while the error-correction pieces mature, keeping the cloud machines improving in parallel.
- Modular processors designed to link to one another, so the architecture learns to span more than a single chip through chip-to-chip connections and short-range couplers.
Each of these is meant to retire a specific risk. One demonstrates the code's layout. Another demonstrates modular connection. Only when those are in hand does the full system become a matter of assembly rather than invention.
What Starling is supposed to be
Starling is described as a machine with around 200 logical qubits capable of running something like 100 million quantum gates, housed across multiple connected modules. That gate count matters more than the headline qubit number. Shallow circuits can be faked or mitigated; deep circuits with tens of millions of operations are where error correction stops being optional. If a machine can actually run that many gates with logical error rates low enough to trust the output, it has crossed from demonstration into tool.
Beyond Starling the roadmap sketches an even larger system intended to reach into the thousands of logical qubits, built from the same modular ideas scaled up. That far horizon is deliberately vaguer, as it should be. The nearer stones carry the weight.
Why take it seriously, and why stay skeptical
Roadmaps are marketing as much as engineering. Target years slip, and a diagram of future chips is not a working machine. IBM's record of shipping the processors it names on roughly the cadence it promised is part of why this particular plan gets attention. The company has repeatedly put hardware on the cloud that matched its earlier slides.
The honest read is that the roadmap is a bet with its risks spelled out. The qLDPC gamble could stumble if the long-range couplers prove too noisy. Modular links could become the bottleneck. But by naming each machine and the single thing it must prove, IBM has made its assumptions legible. If any stone cracks, it will be obvious where. That transparency is the real value of putting a flight plan on paper.
